--- Quote Start ---
no this is the component instantiation. You should have a declaration in your architecture, somewhere before the begin
--- Quote End ---
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ARCHITECTURE full1 OF CHAINE_TOP_LEVEL IS
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TYPE tableau IS ARRAY ( 0 TO 15 ) OF STD_LOGIC_VECTOR( 15 DOWNTO 0);
TYPE tableau1 IS ARRAY ( 0 TO 15 ) OF STD_LOGIC_VECTOR( 22 DOWNTO 0);
SIGNAL Done,DONE_t1,DONE_t2,DONE_t0,DONE_t3 :STD_LOGIC;
SIGNAL tab_residuel,tabDC,tabHadINV: tableau ;
SIGNAL FIFO_OUT :STD_LOGIC_VECTOR( 344 DOWNTO 0);
SIGNAL FIFO_IN :STD_LOGIC_VECTOR(344 DOWNTO 0);
SIGNAL coeff_DC :STD_LOGIC_VECTOR( 22 DOWNTO 0);
SIGNAL usedw:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL tabQTACinv,tabQTDCINV: tableau1 ;
SIGNAL START1,START2,START3,START4:STD_LOGIC;
SIGNAL READ ,full,empty:std_logic;
SIGNAL cp : integer RANGE 0 TO 15;
SIGNAL Mode_16,Mode_4,sel : STD_LOGIC;
SIGNAL Mode : STD_LOGIC;
BEGIN
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