Help with vhdl code

I changed my code like these

Mode,Mode_4,Mode_16: in std_logic; 

Mode,Mode_4,Mode_16: inout std_logic; 

 sel :  in std_logic;

vsim work.chaine_top_level(full1)
#  vsim work.chaine_top_level(full1) 
#  Loading std.standard
#  Loading ieee.std_logic_1164(body)
#  Loading ieee.numeric_std(body)
#  Loading ieee.std_logic_arith(body)
#  Loading ieee.std_logic_unsigned(body)
#  Loading work.intra16x16_type_pkg
#  Loading work.intra_16x16_pkg
#  Loading work.chaine_top_level(full1)
#  Loading work.fsm_chaine(graphe)
# ** Failure: (vsim-3817) Port "sel" of entity "fsm_chaine" is not in the component being instantiated.
#     Time: 0 ns  Iteration: 0  Instance: /chaine_top_level/e_fsm_chaine File: C:/projet/FSM_CHAINE.vhd Line: 18
#  Fatal error in Process line__224 at C:/projet/FSM_CHAINE.vhd line 224
#   while elaborating region: /chaine_top_level/e_fsm_chaine
#  Load interrupted
#  Error loading design

Using inout is not the right approach. Inouts are for tristate buffers not making code work.

Define your input and output ports separately.

Have them on two lines instead of one. One line for inputs, one line for outputs.

Hi, I have a problem with PORT MAP on my FSM_CHAINE.vhd i have

ENTITY FSM_CHAINE is
------------------------------------------------------------------------------------------
   PORT
        ( CLK : IN STD_LOGIC;
          reset : IN STD_LOGIC;   
          START : IN STD_LOGIC;
          start_out : in std_logic;
          DONE_t0: IN STD_LOGIC;
          DONE_t1: IN STD_LOGIC;
          full   : IN STD_LOGIC;
          usedw  : IN STD_LOGIC_VECTOR (3 DOWNTO 0);  
          Mode_4 : IN std_logic;
          Mode_16: IN std_logic;
          --sel :  in std_logic_Vector(0 downto 0);
          sel    :  IN std_logic;
          Mode   : OUT std_logic;
          START1 : OUT STD_LOGIC;
          START2 : OUT STD_LOGIC;
          START3 : OUT STD_LOGIC;  
          READ   : OUT STD_LOGIC;
          DONE   : OUT STD_LOGIC
          );
      
         
        END FSM_CHAINE;
      

ARCHITECTURE full1 OF CHAINE_TOP_LEVEL IS
----------------------------------------------------------- 
TYPE tableau IS ARRAY ( 0 TO 15 ) OF STD_LOGIC_VECTOR( 15 DOWNTO 0);
TYPE tableau1 IS ARRAY ( 0 TO 15 ) OF STD_LOGIC_VECTOR( 22 DOWNTO 0);
SIGNAL Done,DONE_t1,DONE_t2,DONE_t0,DONE_t3 :STD_LOGIC;
SIGNAL tab_residuel,tabDC,tabHadINV: tableau ;
SIGNAL FIFO_OUT :STD_LOGIC_VECTOR( 344 DOWNTO 0);
SIGNAL FIFO_IN  :STD_LOGIC_VECTOR(344 DOWNTO  0);
SIGNAL coeff_DC :STD_LOGIC_VECTOR( 22 DOWNTO  0);
SIGNAL usedw:STD_LOGIC_VECTOR(3 DOWNTO 0); 
SIGNAL tabQTACinv,tabQTDCINV: tableau1 ;
SIGNAL START1,START2,START3,START4:STD_LOGIC;
SIGNAL READ ,full,empty:std_logic;
SIGNAL cp : integer RANGE 0 TO 15;
SIGNAL  Mode_16,Mode_4,sel  : STD_LOGIC;  
SIGNAL Mode : STD_LOGIC;
   BEGIN 

E_FSM_CHAINE :FSM_CHAINE     
   PORT MAP
        ( 
          clk             	   => CLK,
          reset           	   => reset,
          start           	   => START,
          start_out           => START_out,
          START1              => START1,
          START2              => START2,
          START3              => START3,
          DONE_t0             => DONE_t0,
          DONE_t1             => DONE_t1,
          full                => full,
          usedw               => usedw,
          READ                => READ,
          DONE                => DONE_chaine_out ,
          sel                 => sel,
          Mode                => Mode,
          Mode_4              => Mode_4,
          Mode_16             => Mode_16
        );

** Error: C:/projet/CHAINE_TOP_LEVEL.vhd(181): (vcom-1136) Unknown identifier "sel".
** Error: C:/projet/CHAINE_TOP_LEVEL.vhd(182): (vcom-1136) Unknown identifier "mode".
** Error: C:/projet/CHAINE_TOP_LEVEL.vhd(183): (vcom-1136) Unknown identifier "mode_4".
** Error: C:/projet/CHAINE_TOP_LEVEL.vhd(184): (vcom-1136) Unknown identifier "mode_16".
** Warning: C:/projet/CHAINE_TOP_LEVEL.vhd(474): Duplicate signals in sensitivity list.
** Error: C:/projet/CHAINE_TOP_LEVEL.vhd(482): VHDL Compiler exiting

How about your component declaration for FSM_CHAINE in CHANE_TOP_LEVEL.vhd ?