Help with vhdl code

I changed my code like these

Mode,Mode_4,Mode_16: in std_logic; 

Mode,Mode_4,Mode_16: inout std_logic; 

 sel :  in std_logic;

vsim work.chaine_top_level(full1)
#  vsim work.chaine_top_level(full1) 
#  Loading std.standard
#  Loading ieee.std_logic_1164(body)
#  Loading ieee.numeric_std(body)
#  Loading ieee.std_logic_arith(body)
#  Loading ieee.std_logic_unsigned(body)
#  Loading work.intra16x16_type_pkg
#  Loading work.intra_16x16_pkg
#  Loading work.chaine_top_level(full1)
#  Loading work.fsm_chaine(graphe)
# ** Failure: (vsim-3817) Port "sel" of entity "fsm_chaine" is not in the component being instantiated.
#     Time: 0 ns  Iteration: 0  Instance: /chaine_top_level/e_fsm_chaine File: C:/projet/FSM_CHAINE.vhd Line: 18
#  Fatal error in Process line__224 at C:/projet/FSM_CHAINE.vhd line 224
#   while elaborating region: /chaine_top_level/e_fsm_chaine
#  Load interrupted
#  Error loading design