Honored Contributor
Honored ContributorI tried again to check the setup relationship between those clocks, but unfortunately without success.
That is what i wrote in the sdc file: create_clock -period 41.666 -name main_clk_in_24 [get_ports {clk_24_a}] create_clock -period 20.83 -name usb_if_in_clk_48 [get_ports {clk_usb_if}] create_clock -period 25 -name adc_clk derive_pll_clocks set_clock_groups -exclusive -group [get_clocks {u_fpga|RT_acq_digital_design|clk_manage|u_pll|altpll_component|pll|clk[0]}] -group [get_clocks {u_fpga|RT_acq_digital_design|clk_manage|u_pll|altpll_component|pll|clk[2]}] -group [get_clocks {u_fpga|RT_acq_digital_design|clk_manage|u_pll|altpll_component|pll|extclk[0]}] -group [get_clocks {main_clk_in_24}] -group [get_clocks {usb_if_in_clk_48}] \ set_input_delay -clock adc_clk -max 10 [get_ports {adc_b*}] -clock_fall set_input_delay -clock adc_clk -min 5 [get_ports {adc_b*}] -clock_fall I chose "check timing" and got in the report the same columns as before: "Slack", "from node", "to node", launch clock", "latch clock". Are you sure that Quartus 8.0 can show the setup relationship?
