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What about the clock output pin delay and the internal routing delay from the PLL output to the output pin? how can the timequest know those delays? it doesn't know that this virtual clock has also a delay on its way from the pll output to the fpga output (besides the board delay). How can i find those delays?
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The user should provide relation of virtual clk to base clk (at pin of fpga). This has nothing to do with PLL and internal fpga or clk out pin. Just delay from base clk pin at fpga to virtual clk pin on device. The tool needs that and leave the rest for it. The tool will calculate PLL effect as it generates latch clk at the receiving end
In your case your base clk is 24MHz I believe. yet your device clk is 40. I need to see what setup relationship the tool gets. If you get one clk period or so then that is ok . If you are getting zero or very tight then you need multicycle to correct the tool's behavoiur. If unsure about any failure you need to see the relationship as seen by tool and you coud be surprised sometimes. On the other hand there is no point passing timing when the constraints are wrong. and it is unfair when it fails timing but due to incorrect relationship.
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