Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Help with timequest inputs constraints

Hi, I'm trying to define input constraints for an input data bus received by an A2D. The launch clock in the A2D is a derived PLL clock which is sent from the FPGA to the A2D and the latch clock is a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

--- Quote Start ---

There are two scenarios at input to FPGA:

For example in your case virtual clk is late relative base clk by amount of board delay. This way you don't have to calculate things yourself.

--- Quote End ---

What about the clock output pin delay and the internal routing delay from the PLL output to the output pin? how can the timequest know those delays? it doesn't know that this virtual clock has also a delay on its way from the pll output to the fpga output (besides the board delay). How can i find those delays?