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"Your PLL clk(3) sources the ADC and is not the launch clk. The launch clk is that clk(3) as seen at ADC clk input pin (this is not same as clk(3) at fpga)"
Why? i guess that because of the following:
1. The clock's routing from the pll output to the fpga clock output pin.
2. The fpga output pin delay.
3. The board delay.
Is that correct?
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There are two scenarios at input to FPGA:
1) you either receive data with its clock, source synchronous and then set_input_delay is equal to data offset from its clock at fpga pins. So if you know tCO of device and board delays then you can estimate this offset, or actually measure it.
2) use model for launch clk (virtual clk) and enter tCO as given by device data sheet for your set_input_delay relative
Then tell the tool of any time offset between virtual clk and base clk in the waveform description. So you can delay either as required. For example in your case virtual clk is late relative base clk by amount of board delay. This way you don't have to calculate things yourself.
It remains important to find out the setup relationship at failing io
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