Help with timequest inputs constraints

"Your PLL clk(3) sources the ADC and is not the launch clk. The launch clk is that clk(3) as seen at ADC clk input pin (this is not same as clk(3) at fpga)"

Why? i guess that because of the following:

1. The clock's routing from the pll output to the fpga clock output pin.

2. The fpga output pin delay.

3. The board delay.

Is that correct?

"what it needs is relationship of virtual clk to base clk and that is your entry to make on top of input delay setting."

Should the input delay in the constraint be calculated as: source_reg_tCO+pll_to_output_pin_routedelay+output_pin_delay+board_route_delay

?