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There are two PLL clocks- PLL_CLK[2] is the latch clock and PLL_CLK[3] is the launch clock and its shifted in 180 degrees. I tried to set the virtual clock as the launch clock and the setup relationship is still not shown.
How can the timequest know the setup relationship between PLL clock and virtual clock? All it knows about the virtual clock is its frequency (which is identical to the latch clock's frequency) but it knows nothing regarding the phase shift...
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If you declare virtual clock but without any further reference at set_input_delay then it is doing nothing at all and you can delete it.
Your PLL clk(3) sources the ADC and is not the launch clk. The launch clk is that clk(3) as seen at ADC clk input pin (this is not same as clk(3) at fpga)
Your 10 ns tCO is relative to ADC clk pin and it will be wrong to relate it otherwise.
Virtual clk is taken as the launch clk at external device and so your 10 ns relates to virtual clk. Timequest looks at the relationship between virtual clk and base clk that eventually latches at input register (i.e. pll clk(2)) and so it knows about phase details. what it needs is relationship of virtual clk to base clk and that is your entry to make on top of input delay setting.
Try a simple program, set virtual clk as latch clk in terms of phase and speed then set a tiny delay on either and see how faiure is reported.
The use of virtual clk is particularly useful if your data and clk are not coming to fpga in parallel as in your case since you declare virtual clk, set input delat relative to it then leave it to tool to work out relation to latch clk.
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