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Altera_Forum
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11 years ago

Help with timequest inputs constraints

Hi, I'm trying to define input constraints for an input data bus received by an A2D. The launch clock in the A2D is a derived PLL clock which is sent from the FPGA to the A2D and the latch clock is a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

There are two PLL clocks- PLL_CLK[2] is the latch clock and PLL_CLK[3] is the launch clock and its shifted in 180 degrees. I tried to set the virtual clock as the launch clock and the setup relationship is still not shown.

How can the timequest know the setup relationship between PLL clock and virtual clock? All it knows about the virtual clock is its frequency (which is identical to the latch clock's frequency) but it knows nothing regarding the phase shift...