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Altera_Forum
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11 years ago

Help with timequest inputs constraints

Hi, I'm trying to define input constraints for an input data bus received by an A2D. The launch clock in the A2D is a derived PLL clock which is sent from the FPGA to the A2D and the latch clock is a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

No it is not showing it? I noticed your adc data launch clk is from pll according to the TQ report and I also noticed you have set that in your sdc file. The launch clk is the virtual clk not pll clk. PLL clk is the latch. May be that is why setup relationship is not shown in the report.