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Altera_Forum
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11 years ago

Help with timequest inputs constraints

Hi, I'm trying to define input constraints for an input data bus received by an A2D. The launch clock in the A2D is a derived PLL clock which is sent from the FPGA to the A2D and the latch clock is a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I tried that, no setup relationship is shown, it shows the columns "slack", "from node", "to node", launch clock" and "latch clock", you can see it in the attached screen shot. Maybe its because quartus 8.0 is an old version?