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Thanks for your reply, from some reason the timequest doesn't show the setup relationship in the i/o path timing report, the clock skew and data delay are not shown as well (i read the timequest user guide and it seems from its screen shots that those parameters should have been shown). How can i check the setup relationship? I'm using quartus 8.0.
Regarding the multicycle, i think it won't be right since the input data is changed in every clock edge. Maybe i have problems with the clocks definitions? How should I define a clock which is generated by a PLL and sent to an external device which launches the FPGA input data?
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go to tools => timequest => update timing => check top failing paths.
The multicycle will be needed if timequest shows setup relationship less than clk period. This is not multicycle for increasing relationship to > 1clk period but to get it to 1 clk period. Let us first see that relationship then we can try explain results. we are talking about different clocks...
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