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Altera_Forum's avatar
Altera_Forum
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11 years ago

Help with timequest inputs constraints

Hi, I'm trying to define input constraints for an input data bus received by an A2D. The launch clock in the A2D is a derived PLL clock which is sent from the FPGA to the A2D and the latch clock is a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Thanks for your reply, from some reason the timequest doesn't show the setup relationship in the i/o path timing report, the clock skew and data delay are not shown as well (i read the timequest user guide and it seems from its screen shots that those parameters should have been shown). How can i check the setup relationship? I'm using quartus 8.0.

Regarding the multicycle, i think it won't be right since the input data is changed in every clock edge. Maybe i have problems with the clocks definitions? How should I define a clock which is generated by a PLL and sent to an external device which launches the FPGA input data?