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Honored Contributor
Honored ContributorHelp with Finite state machine
Hi guys, as an altera pupil i am still struggling with getting FSM to work properly i wonder if it is my testbench that has a problem or the code itself. This is the idea:
when key_0 is pressed let LEDG(1) light (on) ----closed state when key_1 is pressed let LEDG(0) light (on)-----opened state when key_2 is pressed let LEDR(1) light (on)------locked state when key_3 is pressed it unlocks and enters into error state causing LEDG(1), LEDG(0), LEDR(0) and LEDR(1) to light(all on) This is how my code looks at the moment library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity uppgift_dorr is port( clk : in std_logic; --clock signal reset_n : in std_logic; --reset signal key_0, key_1, key_2, key_3 : in std_logic; LEDR : out std_logic_vector(1 downto 0); LEDG : out std_logic_vector(1 downto 0) ); end uppgift_dorr; architecture Behavioral of uppgift_dorr is --Defines the type for states in the state machine type state_type is (closed,opened,locked,error); --Declare the signal with the corresponding state type. signal Current_State, Next_State : state_type; begin -- Synchronous Process p0: process(clk, reset_n) begin if( reset_n = '0' ) then --Synchronous Reset Current_State <= opened; elsif (rising_edge(clk)) then --Rising edge of Clock Current_State <= Next_State; end if; end process; ----------------------------------------------------------------------------- -- Combinational Process p1: Process(Current_State, key_0, key_1, key_2, key_3) begin case Current_State is when opened => LEDG <= "01"; LEDR <= "00"; if ( key_0 = '0' ) then Next_State <= closed; else Next_State <= opened; end if; when closed => LEDG <= "10"; LEDR <= "01"; if ( key_1 = '0') then Next_State <= opened; elsif (key_2 = '0') then Next_State <= locked; else Next_State <= closed; end if; when locked => LEDG <= "00"; LEDR <= "10"; if ( key_3 = '0') then -- Låser upp dörren Next_State <= closed; elsif(key_2 = '0')then -- tray to lock, error Next_State <= error; else Next_State <= locked; end if; when error => LEDG <= "11"; LEDR <= "11"; Next_State <= error; end case; --end if; end process; end Behavioral; -------------------------------------------- The test bench looks this way: LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY uppgift_dorr_vhd_tst IS END uppgift_dorr_vhd_tst; ARCHITECTURE uppgift_dorr_arch OF uppgift_dorr_vhd_tst IS -- constants -- signals SIGNAL clk : STD_LOGIC := '0'; SIGNAL key_0 : STD_LOGIC; SIGNAL key_1 : STD_LOGIC; SIGNAL key_2 : STD_LOGIC; SIGNAL key_3 : STD_LOGIC; SIGNAL LEDG : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL LEDR : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL reset_n : STD_LOGIC := '0'; COMPONENT uppgift_dorr PORT ( clk : IN STD_LOGIC; key_0 : IN STD_LOGIC; key_1 : IN STD_LOGIC; key_2 : IN STD_LOGIC; key_3 : IN STD_LOGIC; LEDG : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); LEDR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); reset_n : IN STD_LOGIC ); END COMPONENT; BEGIN i1 : uppgift_dorr PORT MAP ( -- list connections between master ports and signals clk => clk, key_0 => key_0, key_1 => key_1, key_2 => key_2, key_3 => key_3, LEDG => LEDG, LEDR => LEDR, reset_n => reset_n ); clk <= NOT clk after 20 ns; -- 50MHz reset_n <= '0', '1' after 100 ns; init : PROCESS -- variable declarations BEGIN key_0 <= '1'; WAIT FOR 50 ns; key_1 <= '1'; WAIT FOR 50 ns; key_2 <= '1'; WAIT FOR 50 ns; key_3 <= '1'; WAIT FOR 50 ns; ------------------------- key_0 <= '0'; WAIT FOR 50 ns; key_1 <= '0'; WAIT FOR 50 ns; key_2 <= '0'; WAIT FOR 50 ns; key_3 <= '0'; WAIT FOR 50 ns; WAIT; END PROCESS init; always : PROCESS -- optional sensitivity list -- ( ) -- variable declarations BEGIN -- code executes for every event on sensitivity list WAIT; END PROCESS always; END uppgift_dorr_arch; ----------------------------------------------------------- Can anyone help?
