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yes that is what I meant. It should be ok on 40MHz speed (usually).
However, I don't get what you are aiming at. It will help if you tell us what you are trying to achieve in terms of concept (not code).
Normally gain word is multiplied by signal and result is then truncated say by 11 bits.
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I really don't know.. I'm just given the equation. You have a 14 bit input and subtract that 14-bit input
from 8192. Then you divide (right shift) by 2^11. Thus, one is essentially subtracting and only keeping
bits 13, 12, 11.
You know, in 'C you can write a statement and then use it as a pointer. You don't have to have
the variable name. You can use an expression. So, it seemed reasonable to me that one could
do the same thing in VHDL. I guess not.
((unsigned(gain_in) - MIN_GAIN) This expression is 14 bits. So why can't one just extract what bits
one wants instead assigning it to a signal name? That way one can avoid using the concurrent
statement altogether.
As I mentioned before. Something like (unsigned(gain_in)-MIN_GAIN)(13 downto 11).
The synthesizer should interpret this as perform the subtraction and from the result take bits
13, 12 and 11. Unfortunately,, ISE doesn't do that. It gives and ERROR. So does Cadence.
But in 'C' one can do something similar.
Honored Contributor
