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You have two stages:
subtraction followed by addition of 1 to those 3 bits
first: it doesn't make much sense as you lose a lot of bits (11 bits set permanently to zero)
second: if you want subtraction and addition in one clock then you might just put one of them outside the clocked process
since either way it implies one clock period for both operations.
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You mean:
Put this outside in a concurrent statement:
val = (unsigned(gain_in) - MIN_GAIN;
Then, in the clocked process put:
gain = b"000" & x"00" & val(13 downto 11);
I did this a little while ago and it appears to work.
The question is: Will the output of val be ready by the time the
clock pulse comes? The clock is 40 MHz in a Virtex 4. That gives 25 ns
to get through the subtractor logic to the gain register.
Cadence simulations shows it's working OK.
But isn't there a way to say you want only some particular
bits in an expression like the above and do it in the clocked
process? (A-B) is an expression giving a result of so many bits.
What's wrong with (A-B)(13 downto 11) meaning that only bits
13 to 11 will be used after the subtraction. Why does it have to
be assigned to some signal?
Thanks,
PWS
Honored Contributor
