Altera_Forum
Honored Contributor
17 years agoHelp with ALTPLL Error
Dear list,
I have used the MegaWizard Plug-In Manager to instantiate an ALTPLL for my Cyclone II device. At some point in my design I began receiving the following Critical Warning: Critical Warning: Implemented PLL "clock:inst2|pll:PLL1|altpll:altpll_component|pll" as Cyclone II PLL type, but with critical warnings Critical Warning: Input frequency of PLL "clock:inst2|pll:PLL1|altpll:altpll_component|pll" must be in the frequency range of 10.0 MHz to 16.67 MHz for locking Critical Warning: Input frequency of PLL "clock:inst2|pll:PLL1|altpll:altpll_component|pll" must be in the frequency range of 10.0 MHz to 16.67 MHz for locking The two inputs referred to are the internal and external clocks, both of which are 10.0 MHz. Is this a genuine critical warning? What if my input frequency is 9.99 MHz? Will the PLL still lock? How do I eliminate this warning? Attached is the generic map from the generated .vhd file. Any unused ports have been removed for brevity: clk0_divide_by => 1, clk0_duty_cycle => 50, clk0_multiply_by => 2, clk0_phase_shift => "0", clk1_divide_by => 1, clk1_duty_cycle => 50, clk1_multiply_by => 1, clk1_phase_shift => "0", clk2_divide_by => 1, clk2_duty_cycle => 50, clk2_multiply_by => 1, clk2_phase_shift => "50000", compensate_clock => "CLK0", gate_lock_signal => "NO", inclk0_input_frequency => 100000, inclk1_input_frequency => 100000, intended_device_family => "Cyclone II", invalid_lock_multiplier => 5, lpm_hint => "CBX_MODULE_PREFIX=pll", lpm_type => "altpll", operation_mode => "NORMAL", port_clkswitch => "PORT_USED", port_inclk0 => "PORT_USED", port_inclk1 => "PORT_USED", port_locked => "PORT_USED", port_clk0 => "PORT_USED", port_clk1 => "PORT_USED", port_clk2 => "PORT_USED", primary_clock => "inclk0", valid_lock_multiplier => 1 Please let me know if I need to post any more relevant information. Thank You, Brian E. Heilig