Help with a VHDL code - using an array

Try and simulate your code, or use signaltap in an FPGA project to see what is happening.

type pigsArray is array (0 to 7) of integer range 0 to limit;

limit is a variable input and can't be used to constrain a type. I don't even understand how this compiled without error. Use a generic for limit instead of an input.

					for checkCounter in 0 to 7 loop 
						exit when ((pigsArray_signal(counter) > pigsArray_signal(checkCounter)) and
							(pigsArray_signal(counter) < (pigsArray_signal(checkCounter) + 26) and
							(counter /= checkCounter)));
					end loop;

I don't understand exactly what you tried to do here, but as is this loop doesn't do anything. It just tests values and exits early if certain conditions are met, but it doesn't change any signal or output, so it is probably removed by the synthesizer.