help to understand the protocol pcm

Hi Radouane,

There is alot around.

In principle it is just ADC/DAC realy. i.e. quantise signal(audio) through ADC then pass in channel thn recover by DAC. Coding of DAC/ADC levels are nonlinear. You got codec on your board, use it, thats all in principle, just

DAC/ADC utilised as long comm technique for audio(telephone)

ADC/channel/DAC one direction

ADC/channel/DAC opposite direction

The analogue audio input will need LPF(anti-alias)

The analogue output signal will need LPF(anti-image)

The nonlinear coding is for having uniform signal/quantisation noise ratio.

remember quantisation(rounding) erorr = 1/2 LSB anywhere on the staircase.

so the effect of error is greatest for low signal values.

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Coding of DAC/ADC levels are nonlinear.

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No, not generally. This is the case with some traditional low resolution PCM codings. But PCM is also a transmission protocol used by 24-Bit audio ADC and DAC, and it's obviously linear coded.

i agree, most audio CODEC's PCM is linear quantized.

perhaps you're thinking of a-law and mu-law?

I was indeed referring to the A & u law of early days (CITT). old age.

If linear, how do they then improve S/N ratio for low signal values?

Hi Altera Guru, i need a help

i'm new to this king of FPGA design development.

We have some DAA modules (PCM highway slaves) and they should be connected to the PCM bus, which physically located on PCB.

PCM bus consists of 4 signals CLK, FSYNCN, Tx and Rx - it is serial transmission and it can have up to 128 timeslots(channels). PCM master should be located in FPGA and controlled by the NiosII.

Actually I have a lot of questions, but more actual are:

How a slave device(see DAA, SLIC) can know in which time slot it transmits a data and how master can extract form the serial stream which data belongs to which slave device?

Generally how master/slaves are controlled, if my slaves are located outside the FPGA and master is located in the FPGA and controlled by NiosII?

I appreciate any help.