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Altera_Forum
Honored Contributor
16 years agoHi Altera Guru, i need a help
i'm new to this king of FPGA design development. We have some DAA modules (PCM highway slaves) and they should be connected to the PCM bus, which physically located on PCB. PCM bus consists of 4 signals CLK, FSYNCN, Tx and Rx - it is serial transmission and it can have up to 128 timeslots(channels). PCM master should be located in FPGA and controlled by the NiosII. Actually I have a lot of questions, but more actual are: How a slave device(see DAA, SLIC) can know in which time slot it transmits a data and how master can extract form the serial stream which data belongs to which slave device? Generally how master/slaves are controlled, if my slaves are located outside the FPGA and master is located in the FPGA and controlled by NiosII? I appreciate any help.