Help to translate verilog to vhdl

Greetings, first to say that I am new to the forum and I really do not know if this is the correct section for this type of questions.

I have limited knowledge in vhdl but I am totally new in verilog. A couple of days ago I try to translate a project from verilog to vhdl, for this I am using a translator, but even so I am finding lines that I can not translate to vhdl (lines 1, 2, 3, 8, 11, 15, 36, 51).

`define SDREADRANGE   16*idx+15:16*idx  // Incrementing indexes within generate below
`define SBUSRANGE     32*idx+31:32*idx  // Incrementing indexes within generate below
`define SDRECRANGE    9*idx+8:9*idx  // Incrementing indexes within generate below
   
generate
  genvar   idx;
  for (idx=0; idx<=31; idx = idx+1)
    begin : sdma_engines
 
    // Create a unique register block address: 32 SDMA engines with 64 bytes each = 2K
    wire i_aen = i_aen_sdma_engines & (i_host_addr[10:6] == idx );
 
 
 
    wire [31:0] sdma_dq = i_sdma_dq[`SBUSRANGE]; 
    wire [8:0]  sdma_record_size = i_sdma_record_size[`SDRECRANGE];
 
 
    // SDMA engines use PTIQ's 8-(31+8)
    wire [7:0] ptiq_number = 8'd8 + idx;
        
 
    g1_sdma_engine U_sdma_engine (
 
      // Clock and Reset
      .i_rst                    ( i_rst                       ),  // input          //
      .i_clk                    ( i_clk                       ),  // input          //
 
      // ======= Local Bus Interface =======
      .i_lclk                   ( i_lclk                      ),  // input          //
      .i_host_addr              ( i_host_addr[5:1]            ),  // input   [5:1]  //
      .i_cs                     ( i_cs                        ),  // input          //
      .i_rnw                    ( i_rnw                       ),  // input          //
      .i_aen                    ( i_aen                       ),  // input          //
      .i_host_data              ( i_host_data                 ),  // input   [15:0] //
      .o_host_data              ( odata_engines[`SDREADRANGE] ),  // output  [15:0] //
      .o_ta                     ( sdma_otas[idx]              ),  // output         //
 
      // Interface to source logic
      .i_sdma_enc               ( i_sdma_enc[idx]             ),  // output         //
      .i_sdma_record_added_tk   ( i_sdma_record_added_tk[idx] ),  // input          //
      .o_sdma_ffren             ( o_sdma_ffren[idx]           ),  // output         //
      .i_sdma_ff_almost_full    ( i_sdma_ff_almost_full[idx]  ),  // input          //
      .i_sdma_dq                ( sdma_dq                     ),  // input   [31:0] //
      .i_sdma_eof               ( i_sdma_eof[idx]             ),  // input          //
      .i_sdma_record_size       ( sdma_record_size            ),  // input    [8:0] //
 
      // Backplane Interface via arbiter. Write fully-formed TLP's
      .o_tlp_request            ( s_request[idx]              ),  // output         //
      .i_tlp_grant              ( s_grant[idx]                ),  // input          //
      .o_tlp_data               ( s_data[`SBUSRANGE]          ),  // output  [31:0] //
      .o_tlp_eof                ( s_eof[idx]                  ),  // output         //
      .o_tlp_wen                ( s_wen[idx]                  ),  // output         //
 
      // ptiq
      .i_ptiq_number            ( ptiq_number                 ),  // input    [7:0] //
      .o_ptiq_dav               ( o_sdma_ptiq[idx]            )   // output         //
 
 
      );
              
    end
endgenerate

Cualquier ayuda es muy bienvenida, gracias de antemano.