Help on virtual Pin logic option

Hi,

As we know, when we compile a design in the Quartus II software, all I/O ports are directly mapped to pins on the targeted device. This I/O port mapping had create problems for a modular/hierachical design because our design had lower-level module that had more I/O ports that may not directly feed a device pin, but may drive other internal nodes. Seeing this situation, we tried to use the virtual pin to accommodate this situation.

However in the help file it state that, ‘This option must be assigned to an input or output pin or it is ignored. The Compiler ignores assignments to bidirectional pins, tri-state pins, or registered I/O elements.”

And our design consists of bidirectional pins, so any advice can provide to me to accommodate the situation above?

Any help would be greatly appreciated,

Thanks

Best regards

Angel