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Altera_Forum's avatar
Altera_Forum
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16 years ago

Help on virtual Pin logic option

Hi, As we know, when we compile a design in the Quartus II software, all I/O ports are directly mapped to pins on the targeted device. This I/O port mapping had create problems for a modular/h...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The problem only arises, when you compile the module as top level entity. You didn't clarify, why you intended to do this.