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Altera_Forum
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9 years ago

Help needed in VHDl code for calculating the I and Q phase component for a ADC signal

Hello all, I am designing a DDC in which I need to calculate the In phase(I) and the Quadrature phase(Q) components of my ADC signal. I know how these components are manually calculated from som...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

I assume you have typing mistakes in your last post as well as in your previous diagram.

I don't want to move away from your original post but I asked about sampling rate after ADC i.e. input to mixer and clock speed there.

By sampling rate I mean data sample rate at its given width (not bit rate).

you also have 8 x something. is your data split up into 8 parallel streams or is that 8 independent channels of data.

Without clear answers I really can't help