Help needed in VHDl code for calculating the I and Q phase component for a ADC signal

I assume you have typing mistakes in your last post as well as in your previous diagram.

I don't want to move away from your original post but I asked about sampling rate after ADC i.e. input to mixer and clock speed there.

By sampling rate I mean data sample rate at its given width (not bit rate).

you also have 8 x something. is your data split up into 8 parallel streams or is that 8 independent channels of data.

Without clear answers I really can't help