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Altera_Forum
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9 years ago

Help needed in VHDl code for calculating the I and Q phase component for a ADC signal

Hello all, I am designing a DDC in which I need to calculate the In phase(I) and the Quadrature phase(Q) components of my ADC signal. I know how these components are manually calculated from som...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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Actually, in the decimation process, I reduce the sampling rate of the ADC signal by performing the decimation by 8, where the mixer output undergoes FIR filtering followed by down sampling by 8. Isn't this enough?

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before decimation(after adc, at mixer) what is your clock speed and what is sampling rate