Help multiplier vhdl

Im feeling pretty generous today. I hate seeing overly complicated case statements.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity prueba2 is
port (
  A         : in  std_logic_vector( (7 downto 0);
  B         : in  unsigned (7 downto 0);
  inicio    : in  std_logic;
  clk       : in  std_logic;
  reset     : in  std_logic;
  q         : out unsigned (2 downto 0);
  resultado : out unsigned (15 downto 0)
);
end prueba2;
architecture behavioral of prueba2 is
signal cuenta : unsigned(2 downto 0);
signal y      : unsigned(15 downto 0);
begin
  multi : process (clk, reset)
  begin
    if reset = '1' then
      y  <= (others => '0');
    elsif rising_edge(clk) then
      if inicio = '1' then
        cuenta <= cuenta + 1;
      end if;
      if A /= x"00" then
        if A( to_integer(cuenta) ) = '1' then
          Y   <= Y + ( resize(B, y'length)*(2**to_integer(cuenta)) );
        end if;
      end if;
    end if;
  end process;
  q         <= cuenta;
  resultado <= y;
end architecture;