Help multiplier vhdl

here is my go without sim and without sign bit output.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all; 
entity prueba2 is
port (
A         : in std_logic_vector (7 downto 0);
B         : in std_logic_vector (7 downto 0);
inicio    : in std_logic;
clk       : in std_logic;
reset     : in std_logic;
q         : out std_logic_vector (2 downto 0);
resultado : out std_logic_vector (15 downto 0)
);
end prueba2;
architecture behavioral of prueba2 is
signal y        : unsigned(15 downto 0);
begin
multi : process (clk, reset)
variable cuenta : unsigned(2 downto 0);
variable temp   : unsigned(15 downto 0);
begin
if reset = '1' then 
   --reset all
elsif clk'event and clk = '1' then
 
   if inicio = '1' then
      cuenta := cuenta + 1;
   end if;
    
   q <= std_logic_vector(cuenta);
    
   temp := (others => '0'); --default
    y <= y + temp;
    
    if cuenta = "000" then --update output
       resultado <= std_logic_vector(y);
    end if;
    
   case cuenta is
    
     when "000" =>
        if A(0) = '1' then
           temp := "00000000"&unsigned(B);
          end if;
     when "001" =>
        if A(1) = '1' then
          temp := "0000000"&unsigned(B)&'0';
        end if;
     when "010" =>
       if A(2) = '1' then
         temp := "000000"&unsigned(B)&"00";
       end if;
     when "011" =>
        if A(3) = '1' then
           temp := "00000"&unsigned(B)&"000";
        end if;
     when "100" =>
        if A(4) = '1' then
           temp := "0000"&unsigned(B)&"0000";
        end if;
     when "101" =>
        if A(5) = '1' then
           temp := "000"&unsigned(B)&"00000";
        end if;
     when "110" =>
        if A(6) = '1' then
           temp := "00"&unsigned(B)&"000000";
        end if;
     when "111" =>
        if A(7) = '1' then
           temp := "0"&unsigned(B)&"0000000";
        end if;
   end case;
end if;
end process;
end behavioral;