Help multiplier vhdl

Thank you kaz, but how can I do that in VHDL??

I know how I have to do the operation, but I don't know how to create the register in VHDL.

Right now, I have this:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.std_logic_unsigned.all;

use IEEE.numeric_std.all;

entity reg_des is

port (

multiplicador: in std_logic;

multiplicando: in std_logic_vector (7 downto 0);

registro7: out std_logic_vector (7 downto 0);

registro6: out std_logic_vector (7 downto 0);

Q7: out std_logic;

resultado: out bit_vector (15 downto 0);

clk: in std_logic;

reset: in std_logic);

end reg_des;

architecture behavioral of reg_des is

begin

reg_des : process (multiplicador, clk, reset)

variable Q : std_logic_vector (8 downto 0);

begin

if reset = '1' then Q:= "000000000";

else

if clk'event and clk = '1' then

for i in 0 to 7 loop

Q(i) := Q(i+1);

if i = 0 then

registro7(7) <= Q(i) and multiplicando(7);

end if;

if i = 1 then

registro7(6) <= Q(i) and multiplicando(7);

registro6 (7) <= Q(i-1) and multiplicando(6);

end if;

if i = 2 then

registro7(5) <= Q(i) and multiplicando(7);

registro6 (6) <= Q(i-1) and multiplicando(6);

end if;

if i = 3 then

registro7(4) <= Q(i) and multiplicando(7);

registro6 (5) <= Q(i-1) and multiplicando(6);

end if;

if i = 4 then

registro7(3) <= Q(i) and multiplicando(7);

registro6 (4) <= Q(i-1) and multiplicando(6);

end if;

if i = 5 then

registro7(2) <= Q(i) and multiplicando(7);

registro6 (3) <= Q(i-1) and multiplicando(6);

end if;

if i = 6 then

registro7(1) <= Q(i) and multiplicando(7);

registro6 (2) <= Q(i-1) and multiplicando(6);

end if;

if i = 7 then

registro7(0) <= Q(i) and multiplicando(7);

registro6 (1) <= Q(i-1) and multiplicando(6);

end if;

if i = 8 then

registro6 (0) <= Q(i-1) and multiplicando(6);

end if;

end loop;

Q(8):=multiplicador;

Q7 <= Q(7);

end if;

end if;

end process;

end behavioral;

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Is this the correct way to do it??

Thank you!