--- Quote Start ---
Hi everyone!
I've some problems with a design, I have to Design an algorithmic state machine to implement a parallel series multiplier for eight-bit numbers encoded in SM (Sign-Magnitude). The multiplying is in a register with parallel output and the multiplier in a shift register of length m with serial output, the first bit to be the least significant. Each bit of multiplier, in his turn, multiplies by multiplying all, so that with operations multiplication is performed.
I've the problem with the shift register with serial output, because I don´t know how to do it!!
I'm learning VHDL right now, and I've never work with this hardware description language.
Please if anyone can help me, I'd be very grateful.
Thank you!!
--- Quote End ---
You need to show what have you done so far and where in design stage you want help.
The 8 bit sign&magnitude can be any value from 0111 1111 to 1111 1111
when you multiply you do that per bit then add up as in primary school multiplication.
You can ignore sign bit as you can conclude that at the end, for demo assume you have:
1) 111 1111
2) 111 1101
thus you multiply 1 by 111 1111 and you get 111 1111 then you multiply by zero which results in zero, shift one bit...
xxxxxxx111 1111
xxxxxx000 0000
xxxxx111 1111
xxxx111 111
xx111 1111
x111 1111
111 1111
------------------------
after 7 multiplications you add all to get result then decide sign bit
Honored Contributor
