1. You have a ripple clock, where the output of a register is used as the clock on another signal(i.e. the main clock ripples through the register). If you can make this a clock enable and keep everything fed by the master clock, you'll be better off and your design will be much easier. Note that ripple clocks are not illegal, people use them quite often and they work, but user's also have designs that fail due to ripple clocks. They basically skew your clock so that transfers to/from this ripple clock domain are more difficult.
2-4. You're not meeting timing. If using the Classic Timing Analyzer, you'll see red tables. Go into the Clock Setup: 'CPLD_OSC' report and the Tco reports and right-click on the first path/s and do a List Paths. You'll get info in the bottom pane. It will have a + sign that allows you to get more info as to why it's failing. Is the requirement what you would expect(i.e. if I have a 100MHz clock, a 10ns requirement makes sense. A 1ns requirement does not). Is there large clock skew(a ripple clock could do this) to the source or destination register. Is the datapath too long. Basically spend a good half hour trying to determine exactly what it's saying. Maybe draw a waveform or schematic. Then, if the info it's telling you doesn't make sense or you don't know how to fix it, come back with more details on the path/s you're analyzing.
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