Help making a timer

http://www.altera.com/literature/ug/ug_embedded_ip.pdf Chapter 28 "Interval Timer Core"

This describes an off-the-shelf timer and from reading the functional description you can get an idea of what is involved. But the bottom line is that it is basically just a counter possibly with a comparison against a programmed value.

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From my understanding Im going to have to use the system clock and and divide it out to a Hz that will benefit me.

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That is more like what you would do with a microprocessor/microcontroller and software: you would program the timer hardware to generate an interrupt at a given frequency (1KHz?) and then write software ISR to manage possibly many software timers (counters) and generate software events when they have expired.

There is nothing stopping you from following that approach, but unless you are short on resources, there is no need for that complication and all of your timers can operate directly from the system clock.

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Can you give more details about the project? Do you use 7 segments displays? A led blinking? Are you using an Altera kit? Do you make your own hardware?

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Ok, so yes we are using an Altera board, and we want the LEDR's above the switches to represent the time remaining on the board. We want the game to last a minute, and there are 18 LEDR's we want to use (The red ones). so one LEDR has to turn off every 60/18= 3+1/3 seconds.

My initial Idea was to divide the clock out to a frequency like 3.333 HZ and then on every Posedge of the clock turn a light off, and count up like time=time+1. so once time>=18, the module would output a signal to terminate the game.

After reading Ted's post it sounds like what I am trying to do is more complicated then I thought. I will give Ted's link a read.

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I post a vhdl that implements a up counter in four 7 segments displays. You may delete de bcd to 7seg decoding and displays multiplexing. Keep the counting section and try to adapt it to your game. Are you using Altera DE1 board?

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Hi, we are working with DE2 boards. We are actually using verilog, but I feel the general context of the code is easily transferable, I will just rewrite it in verilog.