library	ieee;
use		ieee.std_logic_1164.all;
use		ieee.numeric_std.all;

entity	disp_7seg is
	port(
		n_clr : in		std_logic;
		clk : in			std_logic;
		segs : out		std_logic_vector(7 downto 0);
		k : out			std_logic_vector(3 downto 0)
		);
end entity disp_7seg;

architecture disp_fsm of disp_7seg is
	signal	k_reg, k_prox : std_logic_vector(3 downto 0);
	signal	dig_reg, dig_prox : unsigned(14 downto 0);
	signal	dig_tick : std_logic;
	signal	digito : unsigned(3 downto 0);
	
	signal	uni_reg, uni_prox : unsigned(3 downto 0);
	signal	dec_reg, dec_prox : unsigned(3 downto 0);
	signal	cen_reg, cen_prox : unsigned(3 downto 0);
	signal	mil_reg, mil_prox : unsigned(3 downto 0);
	signal	baset_reg, baset_prox : unsigned(9 downto 0);
	signal	uni_tick : std_logic;
	signal	dec_tick : std_logic;
	signal	cen_tick : std_logic;
	signal	mil_tick : std_logic;
begin
	process(n_clr, clk)
	begin
		if ( n_clr = '0' ) then
			k_reg <= "0001";
			dig_reg <= ( others => '0' );
			uni_reg <= ( others => '0' );
			dec_reg <= ( others => '0' );
			cen_reg <= ( others => '0' );
			mil_reg <= ( others => '0' );
			baset_reg <= ( others => '0' );
		elsif ( clk'event and clk = '1' ) then
			k_reg <= k_prox;
			dig_reg <= dig_prox;
			uni_reg <= uni_prox;
			dec_reg <= dec_prox;
			cen_reg <= cen_prox;
			mil_reg <= mil_prox;
			baset_reg <= baset_prox;
		end if;
	end process;
	
	k_prox <= "0010" when ( k_reg = "0001" and dig_tick = '1' ) else
				 "0100" when ( k_reg = "0010" and dig_tick = '1' ) else
				 "1000" when ( k_reg = "0100" and dig_tick = '1' ) else
				 "0001" when ( dig_tick = '1' ) else
				 k_reg;
				 
	dig_prox <= dig_reg + 1 when ( dig_reg < 25000 ) else
					( others => '0' );
				 
	dig_tick <= '0' when ( dig_reg < 25000 ) else
					'1';
					
	baset_prox <= baset_reg + 1 when ( baset_reg < 100 and dig_tick = '1' ) else
					  ( others => '0' ) when ( baset_reg = 100 and dig_tick = '1' ) else
					  baset_reg;
					
				 
	uni_tick <= '0' when ( baset_reg < 100 or dig_tick = '0' ) else
					'1';
					
	dec_tick <= '1' when ( uni_tick = '1' and uni_reg = 9 ) else
					'0';
					
	cen_tick <= '1' when ( uni_tick = '1' and dec_tick = '1' and dec_reg = 9 ) else
					'0';
					
	mil_tick <= '1' when ( uni_tick = '1' and dec_tick = '1' and cen_tick = '1' and cen_reg = 9 ) else
					'0';
				 
	uni_prox <= uni_reg + 1 when ( uni_reg < 9 and uni_tick = '1' ) else
					( others => '0' ) when ( uni_reg = 9 and uni_tick = '1' ) else
					uni_reg;
					
	dec_prox <= dec_reg + 1 when ( dec_reg < 9 and dec_tick = '1' ) else
					( others => '0' ) when ( dec_reg = 9 and dec_tick = '1' ) else
					dec_reg;
					
	cen_prox <= cen_reg + 1 when ( cen_reg < 9 and cen_tick = '1' ) else
					( others => '0' ) when ( cen_reg = 9 and cen_tick = '1' ) else
					cen_reg;
					
	mil_prox <= mil_reg + 1 when ( mil_reg < 9 and mil_tick = '1' ) else
					( others => '0' ) when ( mil_reg = 9 and mil_tick = '1' ) else
					mil_reg;
					

	with k_reg select
		digito <= uni_reg when "0001",
					 dec_reg when "0010",
					 cen_reg when "0100",
					 mil_reg when "1000",
					 ( others => '0' ) when others;
					
	with digito select
		segs <= "10111111" when "0000",
				  "00000110" when "0001",
				  "11011011" when "0010",
				  "01001111" when	"0011",
				  "11100110" when "0100",
				  "01101101" when "0101",
				  "11111100" when "0110",
				  "00000111" when "0111",
				  "11111111" when "1000",
				  "01100111" when "1001",
				  "00000000" when others;
					
	k <= k_reg;
end architecture disp_fsm;