Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Help!! Issue with large adder design!!

Hi, I am trying to build a very large adder, that almost fill all the possible logic elements on the fpga chip, and test it performance. however with the current code, when increase my adder s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

--- Quote Start ---

There are some Quartus II compilation options that doesn't let Quartus optimize your design and transform logic into memory.

Check the options at assignments->settings

--- Quote End ---

yes I can see, but which option is for that? can you tell me more specific?