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Altera_Forum
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13 years ago

Help!! Issue with large adder design!!

Hi, I am trying to build a very large adder, that almost fill all the possible logic elements on the fpga chip, and test it performance. however with the current code, when increase my adder s...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

There are some Quartus II compilation options that doesn't let Quartus optimize your design and transform logic into memory.

Check the options at assignments->settings