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Altera_Forum's avatar
Altera_Forum
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14 years ago

Help! Ignored fast input register assignment

Dear everyone:

I'm learning embeded system design using quartus II 11.0. I created a small design using Qsys on Cyclone IV GX. The componets in my design include Nios II processor, on-chip memory, avalon PLL(200MHz LVDS external clock input and 50MHz output) , clock source, 32-bits input/output PIO and UART.

I instantiate this design in VHDL. The codes are shown below:

--- Quote Start ---

library ieee;

use ieee.std_logic_1164.all;

entity test is

port(

cpu_reset : in std_logic;

sys_clk_in : in std_logic;

input_io : in std_logic_vector (31 downto 0);

output_io : out std_logic_vector (31 downto 0);

uart_tx : out std_logic;

uart_rx : in std_logic

);

end test;

architecture hello_world of test is

component test_sys is

port (

reset_reset_n : in std_logic := 'X'; -- reset_n

pio_out_export : out std_logic_vector(31 downto 0); -- export

pio_in_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export

uart_trx_rxd : in std_logic := 'X'; -- rxd

uart_trx_txd : out std_logic; -- txd

clk_pll_inclk_clk : in std_logic := 'X' -- clk

);

end component test_sys;

begin

u0 : component test_sys

port map (

reset_reset_n => cpu_reset, -- reset.reset_n

pio_out_export => output_io, -- pio_out.export

pio_in_export => input_io, -- pio_in.export

uart_trx_rxd => uart_rx, -- uart_trx.rxd

uart_trx_txd => uart_tx, -- .txd

clk_pll_inclk_clk => sys_clk_in -- clk_pll_inclk.clk

);

end hello_world;

--- Quote End ---

I choosed fast input/output register option in assignments editor. But after compilation, I always get this warning:

"Warning: Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information."

After checking cmpilation report, I find fast input register assigmment is ignored. I searched this problem online and found that fast input regsiter option is only vaild when it is assigned to a input pins that feeds to a register. But I don't understand that and don't know how to check it.

Do you guys have any advices about that?

Thank you.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    The fast input register assignement can only work if the incoming signal is directly clocked (registered) before processing it.

    So you can put this in a fast(=io) register: 

    process(clk)
   begin
   if rising_edge(clk) then
      RegisteredInputSignal<=InputPinSignal;
  end if;
end process;

    But you cannot put this in a io register as the input signal is not directly registered. 

    process(clk)
   begin
   if rising_edge(clk) then
      RegisteredInputSignal<=InputPinSignal1 and SomeOtherSignal;
  end if;
end process;

    In your design the clue is in the (as the code you showed is only a wrapper) test sys module.

    Now is it a problem that you don't use the dedicated io register = fast input register? The answer is NO as long as you meet al timing requirements... but that is another chapter in the book.

    Fast input registers have 2 advantages:

    - if it can be put into a fast register timing closure will be easy as the io is registered first (this is simple to constrain)

    - even if you mess up timing constraints your design will give better reproducable results compilation after compilation. This because this register is always at the same spot with the same routing so the same timing.

    Hope this looooooooooonnnnnnggggggg talk helped?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi, jvov:

    Your reply is really quick.:) And Thank you for your detailed explanation.

    But I still have some questions. The project I described in the first post is an assignment, it askes for system with a 32-bits input/output GPIO with IO flops.

    To my understanding, I need to turn fast input/output registers option on to meet the requirement. Is that correct?

    If it is correct, do I need to create a timing constraint on input IO to aviod ignored assignments warning?

    If it is not correct, what should I do to achieve the project requirement?

    Any advices is welcomed.

    Thank you.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Hi, jvov:

    The 32 input pins all have this assignment warning.

    Since there is no external component for input and output in this project, I just assign 32bits input/output PIO random pins (I didn't use the dedicated pins).

    After compilation I just get ignored assignment warning for input pins, but the fast output registers option works. I don't know what's the problem.

    So do you have any advices? Thank you.

    Regards,

    Xuming
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    Hi, jvov:

    The 32 input pins all have this assignment warning.

    Since there is no external component for input and output in this project, I just assign 32bits input/output PIO random pins (I didn't use the dedicated pins).

    After compilation I just get ignored assignment warning for input pins, but the fast output registers option works. I don't know what's the problem.

    So do you have any advices? Thank you.

    Regards,

    Xuming

    --- Quote End ---

    Hi,

    are you using a reset signal for the registers ? Did you set the fast I/O as an assignment ?

    Kind regards

    GPK