ASubr1New Contributor7 years agoHello, I am using a Altera Stratix® V GX FPGA (5SGXEA7N2F45C2). The default clock frequency is 50MHz. I am using the pin PIN_AW35. Can I change the clock frequency? What is the maximum limit? Thanks
Recent DiscussionsQuartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SGIs Quartus Prime Pro 22.4 Compatible with Stratix 10 NX Series Device?Timing analysis - long combinational pathQuartusPro 25.3 Crashed after using the Signal Tap Logic AnalyzerDuplicate_hierarchy_depth / duplicate_register