Hello, I am using a Altera Stratix® V GX FPGA (5SGXEA7N2F45C2). The default clock frequency is 50MHz. I am using the pin PIN_AW35. Can I change the clock frequency? What is the maximum limit? Thanks

Hi,

The maximum frequency supported by an IO pin is not available data sheet, the pin that is mentioned is the IO clock pin. If you are using the PLL in that PIN the maximum frequency 800Mhz, otherwise have to do the simulation.

Regards,

RS