Hello, I am new to Altera and Quartus and I needed help. I'm using Altera EPM3032ATC44-10 on my hardware development board. I have Quartus II 13.0.

I have a design based on an Altera/Intel EPM3064ALC44-7, so it very similar to yours.

You will use the .pof files to program CPLD devices.

An .sdc file for a CPLD can usually be pretty simple. For my device I use this:

# Input 20MHz reference clock
create_clock -period 50.0 -name CLK [get_ports {CLK}]
 
# Input delays
set_input_delay -clock CLK -max 4.0 [all_inputs]
set_input_delay -clock CLK -min 1.0 [all_inputs]
 
# Output delays
set_output_delay -clock CLK -max 4.0 [all_outputs]
set_output_delay -clock CLK -min 1.0 [all_outputs]

That's it for the .sdc file. I use Quartus 13.0sp1.

Do you run your code thru a simulation testbench? I highly recommend it, it will save a lot of headaches like you are seeing.