Forum Discussion
Altera_Forum
Honored Contributor
10 years agoAs far as I know both multiply and devide are, but devision in one clock cycle needs a big area. It is possible that your FPGA has not enoug space left for that.
As far as I know both multiply and devide are, but devision in one clock cycle needs a big area. It is possible that your FPGA has not enoug space left for that.