--- Quote Start ---
If you can post the errors as well we can help you better.
And I don't know much about verilog but isn't <= a VHDL thing, and does Verilog use assign?
--- Quote End ---
Well i have gotten no compilation errors now (had to fix a few here and there) but now the problem is i need to write a synthesizable code. I'm not sure if u have that kind of thing in VHDL.
N yes Verilog uses assign and "<=" is an unblocking statement for verilog which basically means "=".
Coming back to the synthesizable part,
assign distance_o = (dist_counter * 340/2)
I cant use division. How else can i do this?
Honored Contributor
