Forum Discussion
Altera_Forum
Honored Contributor
10 years agoIf you can post the errors as well we can help you better.
And I don't know much about verilog but isn't <= a VHDL thing, and does Verilog use assign?If you can post the errors as well we can help you better.
And I don't know much about verilog but isn't <= a VHDL thing, and does Verilog use assign?