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CChal's avatar
CChal
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6 years ago

Has anyone managed to program a .jic into an ISSI 128Mbit config program P/N IS25LP128

I am trying to program an ISSI 128Mbit config program using the serial flash loader. My device is an ARRIA V. I have done this for years but recently changed my config device to what I thought was ...
CBATT's avatar
CBATT
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6 years ago

Hi,

I believe that this problem may be solved. If not, here on how we manage to get this memory to work with Quartus 19.1 for write, erase and FPGA initialization.

  1. Open Programmer
  2. Go to File > Convert Programming File
  3. Programming file type, select .jic
  4. Open configuration device using "..."
  5. Select your device family
  6. Create a <<new device>>
  7. Configure according to your memory datasheet
    1. e.g., name: IS25LP128, ID: 17, Density: 128Mb, Single dummy: 8, Quad dummy: 6
  8. Select Micron as Flow template
  9. Change Addressing mode(byte) from each flow tab from 4 to 3
  10. In initialization tab:
    1. Remove everything except Read ID (Command 0x9F), Write Enable (Command 0x06) and Write status register (Command 0x01), keep this flow order
    2. Note that you need a Write Enable before sending other commands, check your memory datasheet for more info
  11. In erase tab:
    1. Change Read flag status register to Read status register
    2. Change Command to 0x05 (ISSI memory uses the READ STATUS REGISTER OPERATION for erase status)
    3. Change Expected data to 0x00
    4. Change Expected data mask to 0x01

I hope this helps.

  • indu_man's avatar
    indu_man
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    3 years ago

    Hi,

    though its an old thread, however we are encountering a similar issue with IS25LP256D flash. This is ISSI 256Mb flash connected with Cyclone IV EP4CGX75 FPGA.

    Using the above guidance I could setup the flash programming using 4-byte address mode (3-byte did not work for me perhaps, due to the larger size flash compared to 128Mb).

    Quartus Programmer v22.1, successfully Programs and can Verify the generated .jic file programming.

    However, the design does not work. When the system is rebooted, the FPGA is not able to load the bitstream from the flash.

    I tired to "Examine" the flash contents in the Quartus Programmer, however after successful examination the output Checksum is different from the file which was programmed.

    Though the program/verify cycle is successful, I still doubt my device which I added using the above procedure.

    Is there a standard (tested/working) device file to generate .jic file for ISSI 256 Mb flash which can use the Cyclone IV flash loader?

    Any other idea where to look for problem is appreciated.

    BR,

    Adnan