"Hard routing constraints could not be satisfied"?

Hi Brad, thanks for the advice.

I used the help's search function instead of right-clicking and I didn't get the above. Strange.

The new PIOs aren't in the same IO bank as any DDIO or DQS logic, so that's probably not it. The bank does have a lot of the address lines for one of the DDRs, but I don't think those are given any special treatment. Plus, removing the SignalTap II instances has solved the problem (for now), so the new PIO and the existing constraints are at least _capable_ of co-existing. And every pin's location is constrained (though no logic is constrained, except for what the PLL, DDR, and Nios II megafunctions constrain themselves), so it's not that the new fit has just moved the pins around.

I should mention that it is entirely plausible that the fit is simply becoming borderline. I'm using almost all of the RAM, LEs, pins, and global clocks in this device.

I don't see any entries for the mentioned signal in either the Assignment Editor or in my SDC file, so it seems like I don't have any control over whatever this hard constraint is. Since I've got a work-around for now, I think I'll leave well enough alone.

Thanks.