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Altera_Forum's avatar
Altera_Forum
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12 years ago

half-band filter implementation

I know this is typical in signal processing implementation. Therefore, is there already an example on how to implementation a half-band filter in Verilog? Thanks in advance.
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Is there a corresponding function from Altera for "DDC_HF2_DSP" in the following code for xilinx?

//* (A+D)*B+C

//14 pipelines

genvar Num;

generate

for (Num = 0; Num <= 11; Num = Num + 1)

begin : U_DDC_HF2_DSP

DDC_HF2_DSP DDC_HF2_DSP

(

//* Inputs

.clk ( Clk ),

.a ( Add_a[Num] ),

.d ( Add_d[Num] ),

.b ( Mult_b[Num] ),

.c ( Add_c[Num] ),

//* Outputs

.p ( Dsp_r[Num] )

);

end

endgenerate