Guidelines to avoid Negative Slack with State Machines

Thanks a lot @josyb and @rsefton for your inputs.

@josyb: Thanks for sharing your VHDL code.

Just a doubt to clear in verilog/VHDL. I see that the outputs are driven within the nextstate logic, and not in synchronous block(@(posedge clk)). I see in the josyb's coding that in the nextstate process() block, you have specified finite number of signals in the sensitivity list. But lets say in a similar scenario in verilog, we have the nextstate always@(*) block , and in presence of any asynchronous input signals, wont the output get corrupted. Is this a safe way of coding(Driving output in the nexstate logic)?.

Have gone through CliffordCummings paper http://www.sunburst-design.com/papers/cummingssnug2003sj_systemverilogfsm.pdf (http://www.sunburst-design.com/papers/cummingssnug2003sj_systemverilogfsm.pdf). Can anyone of you share some content/experience on different coding styles(preferrable verilog) and the hardware(Altera Specific) inferred with each case.

Regards

Jeebu