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Your state machine coding looks fine to me, although I don't care for the split combinational nextstate with registered presentstate style any more. There was a day when synthesis tools needed the help of that coding style, but modern tools don't need it and I find it a bit archaic. I know a lot of books still push that style, but don't believe everything you read.
Bob
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A two- or a three-process state machine is the better approach, unless you have something simple that fits perfectly in the synchronous process.
Back to the main issue: if a state machine is failing timing there are 2 possibilities:
- the required clock frequency is simply too high
- there is too much decision logic in the state transitions
Usually it is the second case. This happens e.g. when you test a large counter for a certain value.
Honored Contributor
