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Jeebu -
Your state machine coding looks fine to me, although I don't care for the split combinational nextstate with registered presentstate style any more. There was a day when synthesis tools needed the help of that coding style, but modern tools don't need it and I find it a bit archaic. I know a lot of books still push that style, but don't believe everything you read.
That aside, do you have the design fully constrained for timing? And is that host machine that your state machine is interacting with in the same clock domain? If not, did you structure the design to handle clock domain crossing on the interface?
Bob
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Dear Bob,
Thanks for the reply,
Yes I m working with the same clock domain. So the framework I m working with, takes care of clock domain crossing.and gives me data in the same clock domain. Can you point me in some direction on how to systematically debug it?.
Sometimes the same code when build, will give positive slack, and sometimes negative slack. How do we reliably implement this state machine without any slack?.
Regards
Jeebu
Honored Contributor
