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Altera_Forum's avatar
Altera_Forum
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14 years ago

Global reset bus

Hi all!

I noticed some warnings about a "global reset bus" in SOPC builder with v10.1 that I had not in v9.1:

With this (http://img204.imageshack.us/img204/4353/sopc.png) SOPC design ("system": 1 NIOS II CPU, 1 DDR3 controller, 1 JTAG UART):

http://img204.imageshack.us/img204/4353/sopc.png

I get these warnings:

--- Quote Start ---

Warning: system: The sopc fabric has a single global reset bus; 3 unneeded reset connections ignored

Warning: system: The global reset bus switch is on; 3 redundant reset connections ignored

--- Quote End ---

They concern

- ddr_controller.soft_reset_n

- cpu.reset_n

- jtag_uart.reset

and disappear if I leave these 3 ports unconnected.

I generated the system

- with these 3 ports unconnected (and no warning)

- with these 3 ports connected (and the 2 warnings)

then I looked into the code.

Indeed, there is no difference. The code generated is the same.

Basically, the reset signal sent to the CPU, the DDR controller and the CPU passes through few modules but basically it is an OR between

- reset_n input of the system

- reset_request output of the CPU JTAG debug module

- reset_request output of the DDR controller

that is resynchronized into ddr.sysclk domain (asynchronous assertion - synchronous deassertion).

Can anyone explain to me why the reset connections are generated even if they are left unconnected into the GUI, i.e. what is the "global reset bus"?

Thanks

Julien

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Hi Julien,

    I am glad to see that you are using SLS IP core because I am working over here in SLS fairely new employee. :)

    This is feature of Q10.1 and by default it is turned on.I m going to try to explain what is global reset according to my understanding in Q10.1.

    Well,In Quartus 9.1 or earlier,you wouldnt get this reset warning because in those version,we were taking care personally about the reset stuff.

    Whereas in Q10.1,they provide one feature of global reset that means if this feature is turned on,whatever the RESET that you are giving to you system (whole system),that will be considered as global reset (i.e reset to all your SOPC components).

    So if you have assigned individual reset to your compoents that will b ignored because global reset is turned on. (In short "ONE RESET SIGNAL FOR ALL COMPONENTS)

    If you disable this global reset then you can assign you own custom reset to components individually then it wont give you any warning but if you dont assign while disabling it then it will be again error/warning.

    Hope this concept will help you little. :)
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    OK I get this :)

    2 questions though:

    - what is SLS?

    - How can I turn the "global reset bus" feature off?

    Thanks

    - Julien
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    SLS is the company named as "system level solution" where i work .we are providing different IP cores.

    First i need to know that in SOPC how did u get clock source? Because in left pane,I can not see anything like clock source.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    "Clock Settings" panel at the top of the window show all the clocks in the system.

    If you click the "add" button a new clock appears in the pannel. You can specify its name and frequency, and its source is "external".

    Pannel also displays clocks that come from components I instanciated (here: from the DDR controller).
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    That is ok i already saw that but how your clock came into system means in SOPC system???

    which is "clock and clock_reset".(your first component)?

    And i feel you are using SOPC builder so it will not show u global settings of the clock but if you use Qsys (new one replacement for the SOPC) then u will b able to see global clock setting
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    "clock" component is a pseudo component that SOPC builder displays for each external clock source when you right-click and select the "Show All" view.

    It does not correspond to a real component, it used used only in the purpose of showing clock and reset interconnections.

    So do you know how to disable global reset bus in SOPC Builder?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    As i said there is a separate option in QYS for disabling the global reset,in SOPC it is not.