Glitch free operation post-mux between two asynchronous clock domains

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Though not sure why you think glitch will occur at mux output without any clock but I suggest synchronising slow signal onto fast clock through two stages then clock the mux with fast clock.

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Like I said before, sampling the ~39MHz signal at the ~270MHz clock is not an option - the resulting jitter is too high when the mux is switched to the signal at the 39MHz domain.

The glitching is from the "mux" not truly existing as a mux, but as a LUT. The LUT is not necessarily stable when it is switching between states. Adding the register stage before the FPGA pin will ensure that there is no glitching.